Senior Design Verification Engineer

Job Description

About the Job:

You'll be involved in developing and deploying state-of-the-art solutions using techniques like UVM, C/C++ co-simulation, system emulation, mixed-mode simulation, and formal verification. Their goal is clear: zero-defect results with the most innovative approach to a broad verification space.

Key Responsibilities:

• Work with a talented team on verification projects using advanced methodologies.
• Develop and deploy verification strategies across a wide range of design complexities.
• Collaborate with engineers to achieve defect-free designs.
• Utilize UVM, C/C++, system emulation, and formal verification techniques.
• Drive innovation in verification practices for improved efficiency and results.

Requirements:

• MSEE/BSEE in Electrical Engineering or Computer Engineering.
• 8+ years of experience: Bring your wealth of experience to the table, or if you're a recent graduate with exceptional academic results, we're excited to mentor you into an amazing career.
• Expertise in UVM verification methodology: You'll bring your knowledge of UVM to develop robust and scalable verification environments that challenge traditional limits.
• Quality-driven mindset: You have an unwavering commitment to excellence, always striving for the best results while ensuring the highest standards of quality and precision.
• Strong collaborator: You thrive in a team environment, valuing open communication and working with others to solve complex problems and drive innovation.
• Bonus points: Experience in video processing and video analytics Fantastic! A passion for general programming Even better! We value diverse skills and interests that complement your verification expertise.

If you're eager to push the envelope in design verification and ready to contribute to a team striving for zero-defects, we want to hear from you!